1. Field of the Invention
The present invention relates to an expanded address bus system and, more particularly, to an expanded address bus system wherein a bus access enable signal is included in address signals supplied to a plurality of expanding devices having various types of expanded address buses.
2. Discussion of Related Art
In a conventional expanded address bus system, an expanded address bus in which an address is kept asserted during an access and an expanded address bus in which the address is updated to an address for the next access during the current access are independently arranged in the system. Accordingly, the number of signal lines of the expanded address buses is undesirably increased.
In other conventional expanded address bus systems in which an expanded address bus has a predetermined address bit width and an expanding device's expanded address bus has a bit width smaller than the predetermined address bit width, i.e., a system having expanding devices with different address bit widths, separate command signal lines are arranged for the respective address bit buses having different address widths. Therefore, the number of signal lines of the expanded address bus system is increased, and the command signal lines, which greatly influence the operating speed for each system, must be provided in sets for address buses having different address bit widths. Therefore, the operating speed of the system is undesirably decreased.